Metal oxide semiconductor field-effect transistor and associated methods

ABSTRACT

A metal oxide semiconductor transistor integrated in a wafer of semiconductor material includes a gate structure located on a surface of the wafer and includes a gate oxide layer. The gate oxide layer includes a first portion having a first thickness and a second portion having a second thickness differing from the first thickness.

FIELD OF THE INVENTION

[0001] The present invention relates to metal oxide semiconductorfield-effect transistors (MOSFETs).

BACKGROUND OF THE INVENTION

[0002] For the purposes of the present invention, the expression “metaloxide semiconductor field-effect transistors” (MOSFET) denotes variousfield-effect transistor structures, each including a wafer ofsemiconductor material, also called the substrate or body, a drainregion and a source region integrated in the wafer, and a gate structureincluding a layer of conductive material separated from the wafer by alayer of insulating material (typically an oxide, such as silicondioxide). It should be noted that the expression “metal oxidesemiconductor” (MOS) is also used for transistors in which the layer ofconductive material of the gate is formed by a layer of dopedpolysilicon, instead of metal. It should also be mentioned that metaloxide semiconductor transistors are also called insulated-gatefield-effect transistors (IGFET, insulated-gate FET), to emphasize thatthe gate electrode is electrically insulated from the wafer or body.

[0003] For example, for the purposes of the present invention the termMOSFET is applied not only to transistors having the standard structure,such as the conventional NMOS and PMOS transistors, but also lateraldouble-diffusion MOSFETs (LDDMOSFET or LDMOSFET), or other possibleMOSFET structures comprising a different number of diffused regionsand/or a different arrangement thereof in the substrate, as well asdifferent combinations of the dopants. It is known that an LDMOSFET,referred to for brevity below as an LDMOS transistor, comprises, inaddition to the drain and gate regions, a body region which is alsodiffused under the gate oxide and a drift region associated with thedrain.

[0004] As is known, one of the parameters characterizing a MOSFET is thebreakdown voltage BV. With reference to LDMOS transistors for example,the breakdown voltage BV is the voltage of the drain electrode at whichthe junction between the drain and body is subject to an avalancheeffect (avalanche breakdown). The breakdown voltage BV is correlatedwith the dopants of the drain (or drift) and body regions and with thecurvature and denser spacing of the lines of potential induced by thegate electrode. In the known art, two different methods are used toobtain sufficiently high values of breakdown voltage (BV) in MOS orLDMOS transistors.

[0005] In the first method, the doping of the drain and body regions isappropriately determined, and, in particular, the doping of the drainregion is reduced. This method has the disadvantage of decreasing theperformance of the transistor, causing an increase in its seriesresistance (Ron). The second conventional method proposes the use of arelatively thick gate oxide layer. This approach has the disadvantage ofreducing the transconductance Gm and the current-carrying capacity ofthe LDMOS transistor, thus decreasing the performance of the transistorin terms of gain.

[0006] In the known art, therefore, in the case of LDMOS transistors,the doping and thickness of the gate oxide must be determined in such away as to provide a compromise between the requirements of a suitablebreakdown voltage, a convenient gain and an adequate series resistance,and this compromise cannot be considered to be wholly satisfactory.

SUMMARY OF THE INVENTION

[0007] An object of the present invention is to provide a metal oxidesemiconductor field-effect transistor which overcomes the limitations ofconventional transistors.

[0008] An object of the present invention is achieved by a metal oxidesemiconductor integrated in a wafer of semiconductor material andcomprising a gate structure located on one surface of the wafer andincluding a gate oxide layer. The gate oxide layer includes a firstportion having a first thickness and a second portion having a secondthickness that is different from the first thickness.

[0009] Another object of the present invention is to provide a methodfor manufacturing such a metal oxide semiconductor field-effecttransistor.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The characteristics and advantages of the present invention willbe more clearly understood from the following detailed description ofexamples of its embodiment provided without restrictive intent, andillustrated in the attached drawings, in which:

[0011]FIGS. 1a to 4 are schematic cross-sectional views illustratingdifferent stages of production of an LDMOS transistor according to aparticular embodiment of the invention;

[0012]FIG. 5 is a schematic cross-sectional view illustrating an LDMOStransistor having silicide surface layers according to a firstembodiment of the invention;

[0013]FIG. 6 is a schematic cross-sectional view illustrating an LDMOStransistor having silicide surface layers according to a secondembodiment of the invention;

[0014]FIG. 7 is a schematic cross-sectional view illustrating anN-channel MOS transistor according to a particular embodiment of theinvention;

[0015]FIG. 8 is a schematic cross-sectional view illustrating aP-channel LDMOS transistor which can be constructed according to themethod of the invention; and

[0016]FIG. 9 is a graph illustrating the variation of thetransconductance and saturation current as a function of the voltage Vgsrelative to an N-channel LDMOS transistor and a P-channel LDMOStransistor according to the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] In the figures to which the following description refers, thesame numerical references will be used to indicate identical or similarelements.

[0018] With reference to FIGS. 1a to 4, a description will be given of aparticular example of a process of manufacturing an LDMOS transistorintegrated in a wafer 30 of semiconductor material according to theinvention. Preferably, the LDMOS transistor of this example is of a typewhich can be used for radio-frequency power applications. However, asmentioned above and as will be evident to persons skilled in the art,the teachings of the present invention are also applicable to MOSFETs oftypes other than those described here by way of example.

[0019] According to the example, the wafer 30 is of the P⁺-P⁻ type, inother words of the type normally used for CMOS platforms, and comprisesa P⁺-type silicon substrate 1 and a P⁻-type epitaxial layer 2 grown onthe substrate by conventional methods. The epitaxial layer 2 forms aseparating surface 10 a between the substrate 1 and an outer surface 1 bopposed to it. The epitaxial layer 2 has a conductivity of the same typeas that of the substrate 1, but smaller than this. For example, in termsof resistivity, the silicon substrate 1 has a resistivity in the rangefrom 1 to 100 mΩ/cm and a thickness in the range from 10 μm to 1000 μm.In a particular example, at the end of the production process thethickness of the substrate 1 is 200 μm. The epitaxial layer 2 has aresistivity which is, for example, in the range from 1 to 100 Ω/cm, andhas a thickness which is, for example, in the range from 1 to 10 μm.

[0020] The method according to the invention comprises the formation ofan insulating gate layer 3 on the surface 10 b. The insulating gatelayer 3 can be made from any suitable dielectric material. For example,the insulating gate layer 3 can be an oxide, particularly silicondioxide. The gate oxide 3 has a non-uniform thickness and comprises afirst portion 4 having a thickness t1 and a second portion 5 having athickness t2 which is different from the thickness t1. As is shownclearly in FIG. 1b, the “thickness of the gate oxide” denotes thedistance between the surface of the gate oxide facing the surface 10 bof the wafer 30 and the opposite surface of the gate oxide. In FIG. 1b,the first portion 4 and the second portion 5 are located on oppositesides of an ideal separating surface S.

[0021] In particular, the thickness t1 of the first portion 4 is greaterthan the thickness t2 of the second portion 5. For example, thethickness t1 is in the range from 20 Å to 500 Å and the thickness t2 isin the range from 10 to 250 Å. Preferably, for radio-frequency powerapplications, the thickness t1 is in the range from 100 Å to 300 Å andthe thickness t2 is in the range from 25 to 150 Å. In one particularexample, the thickness t1 is approximately 180 Å and the thickness t2 isapproximately 70 Å.

[0022] A description is given below (FIGS. 2a-2 e) of a particularlyadvantageous method which can be used, starting with the wafer 30 ofFIG. 1a, to form a gate structure, a body region and a drift region ofthe LDMOS transistor. In particular, according to the example, the gatestructure includes the gate oxide 3 and a layer of conductive gatematerial such as, preferably, a layer of polysilicon. A first layer ofoxide 6, having a thickness t3 in the range from t2 to t1 for example,is formed, preferably by growing, on the surface 10 b of the epitaxiallayer 2. According to the values given above, the layer 6 can have, forexample, a thickness of t3=160 Å.

[0023] The ideal surface S for separating the two portions 4 and 5 ofthe gate oxide 3 is then identified in the surface 6. The surface Sideally separates the first layer of oxide 6 in a first region 6 alocated above the part of the surface 10 b on which the first portion 4of the gate oxide 3 will lie, and a second region 6 b located above thepart of the surface 10 b on which the second portion 4 of the gate oxide3 will lie. The region 6 b of the layer 6 is then removed. This removalcan be carried out, for example, by a conventional photolithographicmethod comprising a stage of forming a photoresist mask and a stage ofchemical etching. In greater detail, the forming of the photoresist maskrequires the use of a layer of photoresist (not shown) placed on asurface 9 of the layer of oxide 6 and the partial irradiation of thisphotoresist with electromagnetic waves (ultraviolet waves or X-rays, forexample) which pass through a suitable photomask (not shown). Theirradiation of the photoresist polymerizes the portion of thephotoresist lying above the first region 6 a of the oxide 6 which is notto be removed.

[0024] Chemical etching is then carried out to remove thenon-polymerized portion of the photoresist and the underlying secondregion 6 b of the oxide layer 6 in such a way as to expose a surface 8of the wafer 30. Finally, the removal of the photoresist is completed. Alayer of oxide 7 is then grown on the surface 8 of the wafer 30 and on asurface 9 of the second region 6 a. This growing stage is carried out insuch a way that the portion of the layer of oxide 7 present on thesurface 8 has a thickness of t2 and the portion of the layer 7 grown onthe surface 9 is such that the layers 6 a and 7 have a combinedthickness of approximately t1. A layer of polysilicon 500, suitablydoped, is then deposited on top of the oxide layer 7, as shown in FIG.2d, in order to make it conductive. A portion of this polysilicon layer500 is designed to form the gate polysilicon of the transistor.

[0025] A first layer of masking made from photoresist 501, or morebriefly a photoresist mask, is then formed on top of the polysiliconlayer 500. This first photoresist mask 501 is produced from a layer ofphotoresist placed on the polysilicon layer 500 and suitably irradiatedwith electromagnetic waves which pass through a suitable photomask insuch a way as to cause the polymerization of some of the portions of thelayer. With the aid of this first photoresist mask 501, the polysiliconlayer 500 is etched, by conventional methods for example, to remove theportion of the polysilicon which is not covered by the polymerizedportions of this mask 501. As shown in FIG. 2a, this etching makes itpossible to form a lateral wall W-S (facing the source side, forexample) of the polysilicon gate layer of the transistor. It should benoted that, after the chemical etching, the first photoresist mask 501and the polysilicon layer 500 have an aperture which exposes a surfaceS1 of the oxide layer 7 having a thickness t2 in the proximity of thelateral wall W-S.

[0026] According to the example, the method continues with a stage offorming a P-type body region 12 which is developed within the epitaxiallayer 2. In particular, the region 12 is formed by ion implantation.Preferably, boron ions are implanted with an ion beam F1 of suitableenergy and density (shown schematically by arrows in FIG. 2a) whichstrikes the surface S1 exposed by the photoresist mask 501, passingthrough the oxide layer 7.

[0027] Advantageously, an inclined implantation is carried out; in otherwords, the wafer 30 is inclined at a suitable angle to the ion beam F1in such a way that the beam of ions can also pass obliquely through thepolysilicon layer 500, but at the same time this polysilicon layer isshielded by the first photoresist mask 501. It should be noted that,advantageously, the first photoresist mask 501 is automatically alignedwith the underlying polysilicon 500 because it is the product of thesame stage of masking (and, in particular, of the same photomask) andetching as that carried out to form the wall W-S.

[0028] This provides a highly accurate alignment between the layers 500and 501, which could not be obtained by forming a separate photoresistlayer on the remaining portion of the polysilicon layer 500 after astage of etching carried out to form the polysilicon 500. The correctalignment of the overlapping layers 500 and 501 makes the execution ofthe inclined implantation highly accurate. This inclined implantation isused to form a body region 12 extending over the desired length(generally fractions of a μm) under the polysilicon layer 500. Oncompletion of the implantation, the first photoresist mask 501 isremoved.

[0029] A second layer of masking made from photoresist 502, or morebriefly a second photoresist mask 502, is then formed on top of thepolysilicon layer 500 (FIG. 3a). This second photoresist mask 502 isproduced from a layer of photoresist placed on the polysilicon layer 500and suitably irradiated with electromagnetic waves which pass through asuitable photomask in such a way as to cause the polymerization of someof the portions of the layer.

[0030] With the aid of this second photoresist mask 502, the polysiliconlayer 500 is etched, by conventional methods for example, to remove theportion of the polysilicon which is not covered by the polymerizedportions of this mask 502. As shown in FIG. 3a, this etching makes itpossible to form a lateral wall W-D (facing the drain side, for example)of the polysilicon gate layer of the transistor. This second etching ofthe polysilicon layer 500 forms a polysilicon gate layer 11. It shouldbe noted that, after etching, the second photoresist mask 502 and thepolysilicon layer 500 have an aperture which exposes a surface S2 of theoxide layer 7 having a thickness t1 in the proximity of the lateral wallW-D. Additionally, the photoresist layer 502 shields the gatepolysilicon 11 and the surface of the oxide layer 7 having a thicknesst2.

[0031] According to the example, the method continues with a stage offorming an N-type drift region 16 which is developed within theepitaxial layer 2. In particular, the region 16 is formed by ionimplantation. Preferably, phosphorus ions are implanted with an ion beamF2 of suitable energy and density (shown schematically by arrows in FIG.3a) which strikes the surface S2 exposed by the photoresist mask 502,passing through the oxide layers 7 and 6 a. In particular, an inclinedimplantation is carried out in a similar way to that described for thebody region 12, in such a way that the ion beam F2 can pass obliquelythrough the gate polysilicon 11, but at the same time this polysiliconlayer is shielded by the second photoresist mask 502. Thus the implantedions can occupy a region extending for several fractions of a pm underthe gate polysilicon 11. It should be noted that, advantageously andsimilarly to the process described for the formation of the body region12, the implantation of the drift region 16 is carried out with the samephotoresist mask 502 as that made for the forming of the polysilicongate layer 11, and therefore with a mask automatically aligned with thelayer 11.

[0032] After the two stages of implantation of the body region 12 andthe drift region 16, a stage of heat treatment is advantageously carriedout to enable the corresponding dopants to be fully diffused andactivated. It should be noted that this heat treatment can be identicalto one of those already specified by the VLSI (Very Large ScaleIntegration) CMOS platform (carried out, for example, at less than 1000°C. and in particular at approximately 900° C.), and can therefore besuch that there is no effect on the electrical characteristics of theCMOS components which can be formed on the said wafer 30. It should benoted that, in the conventional manufacture of LDMOS transistors notintegrated with CMOS devices, the drift and body regions are produced bya diffusion process which requires heat treatment at a high temperature,generally above 1000° C. In the particular method described aboveaccording to the invention, the use of inclined implantation enables thebody region 12 and drift region 16 to be extended under the polysilicon11 even without the heat treatment.

[0033] According to a preferred example of embodiment of the invention,CMOS devices (not shown), such as conventional N- and P-channel MOSFETs,are formed on the wafer in addition to the LDMOS transistor. It is clearfrom the above description that the method according to the invention iscompatible with the parallel formation of CMOS devices on the same wafer30. It should also be noted that the advantages offered by inclinedimplantation and those offered by using the same photoresist layers forforming the polysilicon 11 and the subsequent implantation are alsoconsiderable in the manufacture of an LDMOS with a gate oxide layerhaving a uniform thickness.

[0034]FIG. 3b shows the polysilicon gate layer 11, produced by thedefinition-of the layer 500, and the gate oxide 3 produced after a stageof removal of the photoresist 502 and of the layers of oxide (7 and 6 a)not lying under the polysilicon gate layer 11. In one embodiment of theinvention, the body region 12 has a concentration of dopant impuritiesin the range from 10¹⁶ to 10¹⁹ ions/cm³.

[0035] According to the example described, and as shown in FIG. 3b, theN-type region 18 is then formed, as is usually done for CMOS devices, inother words as an N-type region indicated conventionally by the symbolNldd (region of weak doping) and having, in the example, a doping in therange from 10¹⁵ to 10¹⁹ ions/cm³. The region 18 can be formed in aconventional way, by the formation of photoresist masks, followed by ionimplantation.

[0036] Lateral spacers 13 a and 13 b, illustrated in FIG. 4, arepreferably formed on the lateral walls of the polysilicon gate layer 11and of the gate oxide 3. These lateral spacers are formed by using priorart technologies comprising stages of chemical vapor phase deposition(CVD) of a suitable material, followed by a stage of reactive ionetching. The lateral spacers 13 a and 13 b can consist of any suitableinsulating material such as silicon oxide, polysilicon, or, preferably,silicon nitride. As is known, lateral spacers are commonly used in CMOSprocesses to create less doped areas of the source and drain regions atthe body/drain and body/source junctions, to reduce the electricalfields, and more doped areas of the source and drain regions,automatically aligned with the former areas via the spacers, for moreresistive contacting.

[0037] A source region 14 and a drain region 15, both of the N⁺ type,are then formed within the regions 18 and 16 respectively, by ionimplantation through a photoresist mask, as is usually done for thesource and drain regions of CMOS devices. For example, the source region14, the drain region 15 and the drift region 16 have a conductivity inthe range from 10¹⁵ to 10¹⁹ ions/cm³ or, preferably, in the range from10¹⁶ to 10¹⁸. Typically, the region 18 located on the source side ismore heavily doped than the drift region 16 on the drain side.

[0038] A body contact region 17, of the P⁺ type for example, is formedwithin the source region 14 in a similar way to that described above. Itshould be noted that the signs of the P/N conductivity of the regions 1,2, 12, 14, 17, 18 and 15, 16 and the intensity of the correspondingdoping, expressed by the symbols +/−, can differ from those indicatedabove by way of example and shown in the figures. Moreover, theteachings of the present invention are also applicable to LDMOStransistors having a structure different from that of the CMOS platformdescribed, such as a structure comprising P or N substrates with orwithout buried layers.

[0039] It is important to note that the method described above formanufacturing an N-channel LDMOS transistor on a CMOS platform alsoenables P-channel LDMOS transistors to be manufactured in parallel onthe same wafer 30. In other words, the method according to the presentinvention can be used to form complementary LDMOS transistors on a VLSICMOS platform. A P-channel LDMOS transistor 600 which can be formed bythe method described above is shown in FIG. 8. It will be noted that itslayout is similar to that of the transistor of FIG. 4, except for thesign of the conductivity of some doped regions. In greater detail, thetransistor 600 comprises an N⁺ body region 12′, a P⁺ source region 14′,an N⁺ source contact region 17′, a weakly doped Nldd region 18′, a P⁻drift region 16′, and a P⁺ drain region 15′.

[0040] In particular, the body region 12′ and drift region 16′ can beproduced with the same masks and implantation as those used for the bodyand drain regions 12 and 16 of the N-channel transistor of FIG. 4. Itshould be noted that the method according to the invention which makesuse of inclined implantation enables the doping and the lengths of thebody and drift regions to be defined in such a way as to optimize theperformance of the N-channel or P-channel LDMOS.

[0041] We shall now return to the transistor of FIG. 4, indicated as awhole by 100, in which we can distinguish a first active region 26 and asecond active region 27, which extend from the surface of the epitaxiallayer 2 towards the interior of the said layer. The first active region26 comprises the drain region 15 and the drift region 16. The secondactive region 27 comprises the body region 12, the source region 14, thebody contact region 17 and the N-type region 18 located under the sourcespacer 13 a. The first and second active regions are spaced apart from aregion 25 included in the epitaxial layer 2 in which part of thetransistor's conducting channel will be developed.

[0042] It should be noted that the gate oxide layer 3 extends partiallyover the separating regions 25 and that its first portion 4 is close tothe first active region 26 and its second portion 5 is close to thesecond active region 27. In other words, the first portion 4 is locatedon the “drain side” of the transistor 100, and the second portion 5 islocated on the “source side” of the said transistor. In particular, thefirst portion 4 and the second portion 5 are superimposed, respectively,on at least one part of the first active region 26 and at least one partof the second active region 27.

[0043] In greater detail, the first portion 4 of the gate oxide 3extends in such a way that it is superimposed on the separating region25 and on one part of the drift region 16, and the second portion 5 ofthe gate oxide 3 extends in such a way that it is superimposed on atleast one part of the body region 12. It should be noted that the firstportion 4 of the gate oxide 3, close to the drain region 15, has athickness t1 which can be specified in such a way as to obtain a desiredbreakdown voltage BV. In particular, the breakdown voltage can beincreased by increasing the thickness t1. The breakdown voltage canalways be varied by the selection of the thickness t1, provided that thedoping of the drain and body regions is not such that the value of thebreakdown voltage is predetermined.

[0044] The increase of the breakdown voltage is correlated with anincrease in the distance between the gate polysilicon layer 11 and thefirst active region 26. As this distance increases, there is a decreasein the electrical field responsible for the breakdown which can occur inthe surface area of the epitaxial layer 2 facing the gate oxide 3 andcorresponding to a portion of the polysilicon layer 11 close to thedrain region 16.

[0045] Advantageously, the present invention can be used in the field ofradio-frequency power applications to obtain a breakdown voltage BVwhich is higher than that obtainable with conventional LDMOS transistorshaving uniform oxide. For example, for low-voltage applications, withthe values of the thicknesses t1 and t2 indicated above (180 Å and 70Å), and where the doping of the body region 12 and drift region 16 is ofthe order of 10¹⁷ ions/cm³, breakdown voltages BV in the range from16-20 V have been obtained. For conventional LDMOS transistors withuniform gate oxide, having a thickness of 70 Å, and doping comparable tothat indicated above, a breakdown voltage of approximately 10 V isobtained, in other words one considerably lower than that obtainable byapplying the teachings of the present invention.

[0046] Additionally, the increase in the thickness t1, by permitting alimitation of the surface electrical field, reduces the undesiredgeneration of “hot carriers” and enables the gate-drain feedbackcapacity to be reduced, with a consequent improvement in the performanceof the transistor at high frequency. It should be noted that the secondportion 5 of the gate oxide 3 has a thickness t2 which can be selectedin such away as to obtain a predetermined value of the transconductanceGm of the LDMOS transistor. The value of this transconductance isproportional to the gate-body capacity C_(ox), which is inverselyproportional to the distance between the gate electrode and the bodyregion, in other words to the thickness t₂ of the second portion 5. Inparticular, decreasing the thickness of this portion 5 produces anincrease in the transconductance Gm and, therefore, an improvement inthe performance of the transistor in terms of amplification gain. Forexample, with thicknesses t1 and t2 of 180 and 70 Å respectively, a Gmof approximately 200 mS/mm was obtained, as against approximately 80mS/mm which is obtainable with a uniform thickness according to theprior art, and equal to 180 Å=t1=t2 with equal breakdown voltage.

[0047] The possibility of selecting the thicknesses of the first portion4 and second portion 5 of the gate oxide 3 according to the presentinvention is particularly advantageous. This is because this possibilityenables transistors to be produced with a high breakdown voltage BV anda high transconductance, or, at any rate, makes it unnecessary to accepta decrease of the transconductance Gm of the transistor to achievedesired values of the breakdown voltage. By applying the teachings ofthe invention, it is possible to achieve a dual function of increasingthe transconductance Gm while maintaining the breakdown voltage BV atsatisfactory levels.

[0048] Advantageously, the method according to the invention providesstages of formation of silicide on suitable surfaces of the wafer 30 ofFIG. 4. In FIG. 4, the reference numbers 19 and 20 indicate a first anda second area respectively, corresponding, respectively, to the surfaceof the first active region 26 and that of the second active region 27.FIG. 5 shows a transistor 200 with a structure similar to that of thetransistor 100. The transistor 200 comprises surface layers of silicide21, 22 and 23, formed, respectively, on the surface of the gatepolysilicon 11, on the first active area 19 and on the second activearea 20. The surface layers 21, 22 and 23 are, for example, formed fromtitanium silicide (TiSi₂), cobalt silicide (CoSi₂) or tungsten silicide(WSi₂) The siliciding of the surfaces of the gate 11 and of the activeareas 19 and 20 has the advantage of decreasing their surfaceresistivity while improving the performance of the transistor.Preferably, the siliciding is carried out by the conventional methodknown as self-aligned siliciding, or formation of a “salicide” (acronymof “self-aligned silicide”) which permits the formation of layers ofsilicide aligned with the underlying regions of silicon or polysilicon(salicidizing). For example, the layers of silicide 21, 22 and 23 areformed by a stage of deposition (by spraying or “sputtering”, forexample) of a thin layer of a refractory metal over the whole surface ofthe wafer 30, and in particular over the active areas 19 and 20 and onthe surface of the polysilicon layer 11.

[0049] The wafer 30 is then subjected to heating, allowing a chemicalreaction to take place between the deposited metal and the underlyingsilicon, resulting in the formation of the three regions of silicide 21,22 and 23. Preferably, the metal used for siliciding is titanium orcobalt. For tungsten silicide, direct deposition of WSi₂ on thepolysilicon 11 can be used, instead of the self-aligned silicide method.It should be noted that the transistor 200, provided with the threelayers of silicide 21, 22 and 23, has a particularly good performance,since the resistances of the gate, source and drain electrodes aresignificantly reduced. It should also be noted that the transistor 200can have a sufficiently high breakdown voltage BV as a result of beingdesigned with a suitable thickness t1, without significant losses interms of transconductance.

[0050]FIG. 6 shows a transistor 300 according to a further embodiment ofthe invention. In the transistor 300, the first active area 19 of thefirst active region 26 is only partially silicidized. In greater detail,the transistor 300 comprises a layer of silicide 24 extending over thedrain region 15 but not over the portion of the drift region 16 closestto the gate structure. The transistor of FIG. 6 provides a breakdownvoltage BV, for the same thickness of the first portion 4, greater thanthat obtainable with the transistor 200. This is due to the fact thatthe siliciding of the first active region is only partial, and thereforeincreases the “distance” between the surface of the gate polysilicon 11and the more conductive area of the first active region 26, thusreducing the value of the electrical field which can be formed in theepitaxial layer 2 in the proximity of the gate oxide layer 3 on the sideof the drain 16, for the same applied voltage. The increase in thebreakdown voltage BV due to the partial siliciding is possible if thedoping of the drift region is not so high as to impose a value of thebreakdown voltage BV which cannot be modified.

[0051] The structure of FIG. 6 not only provides a high breakdownvoltage, but also offers high performance (a high transconductance Gmfor example), since the resistance of the layers of silicide 21, 22 and24 is reduced in any case. It should be noted that the considerableadvantages in terms of breakdown and performance offered by partialsiliciding as shown in the solution of FIG. 6 can also be obtained forLDMOS transistors which use a gate oxide layer of the conventional type,in other words one of uniform thickness.

[0052] The transistor 300 can be produced from the transistor 100 byforming a protective or shielding element 36. In particular, theshielding element 36 is formed from electrically insulating materialsuch as an oxide, and preferably a silicon oxide. For example, theforming of the element 36 comprises the formation of an oxide layer (notshown) over the surface of the transistor 100, the forming of a layer ofphotoresist positioned over this oxide layer, and the partialirradiation of this photoresist with ultraviolet rays through a suitablephotomask to cause its polymerization.

[0053] Chemical etching is then carried out to remove suitable portionsof the layer of photoresist and of the underlying oxide. The chemicaletching forms the oxide element 36 which is positioned in such a way asto shield at least the part of the first active area 19 which is to bekept free of silicide. In particular, the precision achievable by theoxide masking process described above is such that it is possible toprevent the oxide from covering only the desired portion of the firstactive region 19. In this case, as shown in FIG. 6, the oxide element 36also extends over part of the surface of the gate polysilicon 11.

[0054] After the formation of the oxide element 26, the layers ofsilicide 21, 22 and 24 are formed in a similar way to that describedabove with reference to the transistor 20 (sputtering of the metal,followed by heat treatment). The oxide element 36 shields the underlyingportion of the first active area 19, which is therefore not covered bythe refractory metal during the sputtering. The oxide element 36 alsoacts as a lateral spacer. It should be noted that the method describedabove for the partial siliciding of the active area 19 for the LDMOStransistor is particularly advantageous where the LDMOS transistor 300is integrated in the wafer 30 with CMOS devices. This is because, forconventional CMOS devices, there is a known method of using totalsiliciding of the active area and of the gate polysilicon. Theaforementioned method, in which the protective element 36 is used,enables the total siliciding of the CMOS devices to be carried outsimultaneously with the partial siliciding for the LDMOS device formedin the same wafer.

[0055] Additionally, it is possible to apply in an advantageous way theprocess of total or partial siliciding of active areas 19′ and 20′(similar to the active areas 19 and 20) and of the polysilicon layer 11′to the P-channel LDMOS transistor 600 of FIG. 8, in a similar way tothat described with reference to FIGS. 5 and 6. In particular, in thepartial siliciding of the active area 19′, the portion of the activearea 26′ close to the polysilicon layer 11′ is kept free of silicide,via a protective element similar to the element 36.

[0056] Additionally, computer simulation was used to compare theperformance in terms of saturation current Ids and transconductance Gmof an N-channel LDMOS transistor similar to that of FIG. 6 (in otherwords, having partial siliciding) with that of a P-channel LDMOStransistor, similar to that of FIG. 8, having partial siliciding of theactive area 19′. With reference to this comparison, FIG. 9 shows thevariation of the gate-source voltage (Vgs) due to the simulation of thetransconductance of the N-channel transistor (curve Gm-N), thetransconductance of the P-channel transistor (curve Gm-P), the Idscurrent of the N-channel transistor (curve Ids-N), and the Ids currentof the P-channel transistor (curve Ids-P). These variations wereobtained for a drain-source voltage (Vds) of 5 V.

[0057] It should be noted that the threshold voltages Vt for bothtransistors are very similar, being approximately 0.5 V in each case. AnN-channel transistor of the type shown in FIG. 6 was also constructedand tested, showing a performance closely matching that found by thesimulations. In particular, a cut-off frequency of more than 20 GHz wasmeasured. For the P-channel transistor, since the cut-off frequency iscorrelated with the maximum transconductance and the gate capacities,which can be considered similar to those of the N-channel transistor,the cut-off frequency for the P-channel transistor can be estimated asapproximately 14-15 GHz. Additionally, since the same parameters for theimplantation of the doped regions were assumed for the simulation whichwas conducted, the P-channel transistor can be considered to have abreakdown voltage of 15 V, in other words a value similar to that of theN-channel transistor.

[0058] As stated above, the present invention is also applicable toconventional P-channel or N-channel MOS transistors which can be formedon the same wafer 30 or on a different wafer. In relation to the above,in FIG. 7 the number 400 indicates an example of an N-channel MOStransistor according to the present invention. The transistor 400comprises the wafer 30, a first and a second active region 33 and 34, agate oxide layer 32 formed over a surface 45 of the epitaxial layer 2, alayer of conductive material 35 (polysilicon or metal, for example) andtwo lateral spacers 36 a and 36 b. The first active region 33 comprisesa drain region 37 which is strongly doped (N⁺) and a region 38 which isweakly doped (N⁻). The second active region 34 comprises a source region39 which is strongly doped (N⁺) and a region 40 which is weakly doped(N⁻).

[0059] The gate oxide layer 32 has a first portion 41 having a firstthickness T1 and a second portion 42 having a second thickness T2 whichis different from the thickness T1. In particular, the first portion 41is close to the first active region 33, and its thickness T1 is greaterthan the thickness T2. The first portion 41 of the gate oxide 32advantageously has a thickness such that it is possible to obtainbreakdown voltages higher than those of conventional MOS transistorsusing a gate oxide with uniform thickness. With reference to thetransconductance Gm of the transistor 400, it should be noted that byusing different thicknesses of the gate oxide the value of the breakdownvoltage can be increased at a cost in terms of transconductance which issmaller than the cost incurred when the uniform thickness is increasedwith the thickness of the gate oxide in a conventional MOS.

[0060] Additionally, the process of siliciding the polysilicon layer 35,a first active area 33 including the surfaces of the regions 37 and 38,and a second active area 34 including the surfaces of the regions 39 and40 can also be applied to the transistor 400, in a similar way to thatdescribed with reference to FIGS. 5 and 6. In particular, it is possibleto arrange for the first active area 33 to be only partiallysilicidized. For example, the weakly doped region 38 can be kept free ofsilicide by using a protective oxide element (not shown) similar to theelement 36 of FIG. 6.

[0061] The method of manufacturing the transistors 100, 200, 300, and400 is completed with the formation of suitable metallic contacts (notshown) on the corresponding drain and source regions, and on the bodycontact region if present. Clearly, a person skilled in the art mayfurther modify and vary the method and transistors according to thepresent invention, in order to meet contingent and specificrequirements, all such modifications and variations being includedwithin the scope of protection of the invention as defined by thefollowing claims.

That which is claimed is:
 1. Metal oxide semiconductor transistor (100;200; 300; 400; 600) integrated in a wafer of semiconductor material (30;31) and comprising a gate structure (3, 11; 32, 35) located on onesurface (10 b; 45) of the said wafer and including an insulating gatelayer (3; 32), characterized in that the said insulating gate layer (3;32) includes a first portion (4; 41) having a first thickness (t1; T1)and a second portion (5; 42) having a second thickness (t2; T2)differing from the first thickness.
 2. Transistor (100; 200; 300; 400)according to claim 1, comprising a first active region (26; 33)including a drain region (15; 37) and a second active region (27; 34)spaced apart from the first active region and including a source region(14; 39), the said first and second active region being integrated inthe wafer (30), the first portion (4; 41) of the insulating gate layerbeing close to the first active region, and the second portion (5; 42)being close to the second active region.
 3. Transistor (100; 200; 300;400) according to claim 2, in which the first thickness (t1; T1) of thefirst portion (4; 41) is greater than the second thickness (t2; T2) ofthe second portion (5; 42).
 4. Transistor (100; 200; 300) according toclaim 2, in which the first portion (4) and the second portion (5) ofthe gate insulation ((3) are superimposed, respectively, on at least onepart (16) of the first active region (26) and at least one part (12) ofthe second active region (27).
 5. Transistor (100; 200; 300; 400)according to claim 1, in which the said first thickness (t1; T1) isspecified in such a way as to provide a predetermined value of thebreakdown voltage of the transistor.
 6. Transistor (100; 200; 300)according to claim 1, in which the said second thickness (t2; T2) isspecified in such a way as to provide a predetermined value of thetransconductance of the transistor.
 7. Transistor (100; 200; 300)according to claim 1, in which the said transistor is a lateraldouble-diffusion MOS.
 8. Transistor (400) according to claim 1, in whichthe said transistor is a MOS.
 9. Transistor (100; 200; 300) according toclaim 7, in which the second active region (27) comprises a body region(12) and the second portion (5) of the gate insulation (3) issuperimposed on at least one part of the body region (12). 10.Transistor (100; 200; 300; 400) according to claim 1, in which the saidgate structure (3; 32) comprises a layer of electrically conductivematerial (11; 35) positioned on the gate oxide layer (3; 32). 11.Transistor (200; 300) according to claim 10, in which the said layer ofelectrically conductive material (11) is made from polysilicon and isprovided on one of its surfaces with a layer of silicide (21). 12.Transistor (200; 300) according to claim 10, in which the said first(26) and second (27) active regions extend from the surface of the wafer(30) of semiconductor material towards the interior of the said waferand comprise, respectively, a first (23; 24) and a second (22) silicidesurface layer.
 13. Transistor (300) according to claim 12, in which thefirst silicide surface layer (24) only partially covers the said firstactive region (26).
 14. Transistor (300) according to claims 2 and 13,in which the first silicide surface layer (24) is such that it covers atleast the said drain region (15) and is interrupted in such a way that asurface area of the first active region (26) close to the first portion(4) of the gate oxide is not covered with silicide.
 15. Transistor (200;300) according to claim 12, in which the said silicide belongs to thegroup comprising titanium silicide (TiSi₂), cobalt silicide (CoSi₂), andtungsten silicide (WSi₂).
 16. A transistor (100; 200; 300; 400; 600)according to claim 1, in which the said wafer of semiconductor material(30) comprises a substrate (1) having a first type of conductivity andan epitaxial layer (2) having a conductivity of the first type, theepitaxial layer having a conductivity lower than the conductivity of thesubstrate.
 17. Method for manufacturing a metal oxide semiconductorfield-effect transistor (100; 200; 300) integrated in a wafer (30) ofsemiconductor material, the said method comprising a stage of forming alayer of gate oxide (3) on one surface (10 b) of the said wafer;characterized in that the said layer of gate oxide (3) includes a firstportion (4) having a first thickness (t1) and a second portion (5)having a second thickness (t2) differing from the first thickness. 18.Method according to claim 17, in which the said stage of forming thegate oxide (3) comprises a stage of selecting the first thickness (t1)in such a way as to obtain a specified breakdown voltage of thetransistor, the said first thickness being greater than the secondthickness.
 19. Method according to claim 18, in which the said formingthe gate oxide (3) comprises a stage of selecting the second thickness(t2) in such a way as to obtain a specified value of transconductance ofthe transistor, the said second thickness being smaller than the firstthickness.
 20. Method according to claim 17, in which the saidinsulating gate layer (3) is a layer of oxide and the stage for formingthe gate insulation (3) comprises the stages of: forming a first layerof oxide (6 a, 6 b) on the surface of the said wafer (30), the saidfirst layer of oxide having a thickness (t3) in the range from thesecond thickness to the first thickness, a portion (6 b) of the saidfirst layer of oxide is removed to expose a region (8) of the surface ofthe said wafer (30), a second layer of oxide (7) is grown on the saidregion (8) of the surface of the wafer (30) and on a remaining portion(6 a) of the first layer of oxide positioned on the said region (8) ofthe surface of the wafer (30) having a thickness essentially equal tothe second thickness (t2) and a further portion of the said second layerof oxide (7) being such that the total thickness of the said furtherportion of the second layer of oxide (7) and the said remaining layer ofoxide (6 a) underlying it is essentially equal to the first thickness(t1), delimiting the said insulating gate layer (3) formed in oxide, byremoving a portion of the second layer (7) of the region (8) of thesurface of the wafer (30) and portions (6 a) of the superimposed firstlayer of oxide (6) and second layer of oxide (7).
 21. Method accordingto claim 17, additionally comprising a stage of forming in the wafer(30) a first active region (26), including a drain region (15), and asecond active region (27) spaced apart from the first region andincluding a source region (14), the first portion (4) and the secondportion (5) of the gate oxide (3) being close, respectively, to thefirst region (26) and to the second region (27).
 22. Method according toclaim 21, in which the said transistor is a lateral double-diffusionMOSFET and in which the stage of forming the first (26) and the second(27) active region comprises a stage of forming a drift region (16) anda body region (12).
 23. Method according to claim 17, in which the saidtransistor is a MOS transistor.
 24. Method-according to claim 22, inwhich the said active region extends at least partially under the saidsecond portion (5).
 25. Method according to claim 17, additionallycomprising the stage of forming a layer of conductive material (11) overthe said layer of gate insulation (3).
 26. Method according to claim 21,additionally comprising a stage of forming a first layer of silicide(23; 24) on at least one portion of a first surface (19) of the saidfirst active region (26) and a second layer of silicide (22) on a secondsurface (20) of the said second active region (27).
 27. Method accordingto claim 26, in which the first silicide surface layer (24) onlypartially covers the said first active region (26).
 28. Method accordingto claim 27, in which the first silicide surface layer (24) is formed insuch a way that it covers at least the said drain region (15) and isinterrupted in such a way that an area of the surface of the firstactive region (26) close to the first portion (4) of the gate oxide isnot covered with silicide.
 29. Method according to claim 27, in whichthe said silicide layer is produced by the method of self-alignedsiliciding.
 30. Method according to claim 28, in which the stage offorming the first silicide layer comprises the stages of: forming ashielding element (36) on the said area of the surface of the firstactive region, depositing a refractory metal on at least the said drainregion (15), applying heat treatment to the wafer (30) in such a way asto form the said first silicide layer (24).
 31. Structure integrated ina wafer (30) of semiconductor material, the said structure comprising:at least one MOS field-effect transistor (400) including an activeregion (37, 38) which forms an active area (33) on a surface of thewafer, and a silicide surface layer which at least partially covers thesaid first active area, characterized in that it also comprises at leastone LDMOS transistor (300) including a first active region (26) whichforms a first active area (19) on the surface of the wafer, and a firstsilicide surface layer (24) which only partially covers the said firstactive area.
 32. Structure according to claim 31, in which the saidLDMOS field-effect transistor (300) comprises a gate structure (3, 11)and the said first active region (26) of the LDMOS transistor (300)comprises a drain region (15) and a drift region (16), the said firstsilicide surface layer (24) being such that it covers the drain region(15) and is interrupted in such a way that a portion of the drift region(16) close to the said gate structure (3, 11) is not covered withsilicide.
 33. Structure according to claim 32, in which at least oneelectrically insulating element (36, 13 b) is positioned on one surfaceof the said non-silicide-covered portion of the drift region (16). 34.Structure according to claim 32, in which the said gate structure (3,11) comprises a layer of conductive gate material (11) superimposed onan insulating gate layer (3) positioned on the surface of the wafer(30), and in which the said LDMOS transistor (300) comprises a secondactive region (27) including a body region (12) and a source region(14), each of the said conductive gate layer (11) and the said secondactive region (27) being covered with a corresponding layer of silicide.35. Structure according to claim 34, in which the said insulating gatelayer (3) includes a first portion (4) having a first thickness (t1) anda second portion (5) having a second thickness (t2) differing from thefirst thickness.
 36. Structure according to claim 35, in which the firstthickness (t1) of the first portion (4) of the gate insulation (3) isgreater than the said second thickness, the said first portion beingclose to the drift region (16) and the said second portion being closeto the body region (12).
 37. Structure according to claim 31, in whichthe said wafer of semiconductor material (30) comprises a substrate (1)having a first type of conductivity and an epitaxial layer (2) having aconductivity of the first type, the epitaxial layer having aconductivity which is less than the conductivity of the substrate andthe said first (26) and the said second (27) active region being formedwithin the said epitaxial layer.
 38. Method of manufacturing at leastone MOS field-effect transistor (400) and at least one LDMOSfield-effect transistor (300) integrated in a wafer (30) ofsemiconductor material, the said method comprising the stages of: a)forming in the wafer (30) two active regions (37, 38, 39, 34) of thesaid at least one MOS transistor (400), the said active regions formingcorresponding active areas (33, 34) on the surface of the wafer, b)forming in the wafer (30) a first (26) and a second (27) active regionof the said at least one LDMOS transistor (300), the said first andsecond active regions forming a first and a second active area (19; 20)on a surface of the wafer, c) forming a layer of silicide on at leastone portion of each of the two active areas (33, 34) of the said atleast one MOS transistor (600), d) forming a first (24) and a second(22) layer of silicide on the said first (19) and second (20) activearea of the at least one LDMOS transistor (300), the said first layer ofsilicide (24) only partially covering the first active area (19). 39.Method according to claim 38, additionally comprising the stages of:forming on the wafer (30) a gate structure (3, 11) of the said at leastone LDMOS transistor (300), the said gate structure including aninsulating gate layer and a layer of conductive gate material (11);forming a further layer of silicide (21) on a surface of the layer ofinsulating gate material (11).
 40. Method according to claim 39, inwhich the said first active region (26) comprises a drain region (15)and a drift region (16), and the said second active region comprises abody region (12) and a source region (14), the said stage d) comprisinga stage of: e) forming the first layer of silicide (24) in such a waythat it covers the drain region (15) and in such a way that a portion ofthe drift region (16) close to the said gate structure (3, 11) is notsilicidized.
 41. Method according to claim 40, in which the said stagee) comprises the stages of: shielding the said portion of the driftregion (16) by means of a protective element (36) located at least onthe said portion, depositing a layer of refractory metal on the firstactive area (19), on the second active area (20) and on the shieldingelement (36), carrying out a heat treatment of the wafer (30) in such away that the layer of refractory metal reacts with portions of the firstand second active area on which it is deposited to form silicide. 42.Method according to claim 41, in which the said stage of shielding theportion of the drift region (16) comprises the stages of forming a layerof protective material on the wafer (30) and delimiting the saidprotective element (36) by stages of masking and etching the layer ofprotective material.
 43. Method according to claim 40, in which the gatestructure (3, 11) of the at least one LDMOS transistor (300) comprisesan insulating gate layer (3) positioned on the wafer (30) and includinga first portion (4) having a first thickness (ti) and a second portion(5) having a second thickness (t2) which is less than the firstthickness, the said first portion being close to the drift region (16).44. Method according to claim 40, in which the said stage of forming thegate structure (3, 11) includes the stages of: forming at least oneoxide layer (7, 6 a) on the surface of the said wafer (30), a portion ofthe said oxide layer being designed to form the insulating gate layer(3); forming a layer of polysilicon (500) on a surface of the said oxidelayer (7, 6 a), a portion of the said layer of polysilicon beingdesigned to form the layer of conductive gate material (11), forming afirst masking layer (501) over the said layer of polysilicon to allow afirst stage of etching to be carried out in such a way as to form atleast a first lateral wall (W-S) of the said layer of conductive gatematerial (11) and a first aperture in the layer of polysilicon, removingthe first masking layer and forming a second masking layer (502) overthe said layer of polysilicon (500) to allow a second stage of etchingto be carried out in such a way as to form at least a second lateralwall (W-D) of the said layer of conductive gate material (11) and asecond aperture in the layer of polysilicon.
 45. Method according toclaim 44, additionally comprising the stages of: stages of inclined ionimplantation (F1; F2) through the first aperture of the said first mask(501) and through the second aperture of the said second mask to formthe body region (12) and the drift region (16), the said inclined ionimplantation enabling the body regions (12) and the drift regions (16)to be extended into the wafer (30) at least partially under the gatestructure (3, 11).
 46. Method according to claim 45, in which, after theion implantation stage, a heat treatment is applied to the wafer (30) topermit a further diffusion and activation of the drift (16) and body(12) regions.
 47. Method according to claim 46, in which the said heattreatment is applied at a temperature of less than 1000° C.
 48. Methodaccording to claim 47, in which the said first (501) and second (502)masking layer are formed from photoresist and by irradiation withelectromagnetic waves through a corresponding photomask.
 49. Methodaccording to claim 38, in which the said at least one LDMOS transistorcomprises an N-channel LDMOS transistor (300) and a P-channel LDMOStransistor (600).
 50. Method according to claims 48 and 49, in which thesaid N-channel transistor (300) and P-channel transistor (600) are bothproduced by ion implantation in the wafer (30) through the apertures inthe said first masking layer (501) and in the said second masking layer(502).